Apparatus and method for handling memory access requests
US12430032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.