Low-latency code fetching from memory
US12430079B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Sep 28, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may respond to two types of read commands. When the memory device receives a first type of read command, the memory device may read data from a memory array beginning at an address indicated in association with the received read command. When the memory device receives a second type of read command, the memory device may begin reading data from a cache in the memory device. Data that is read from the memory array may also be stored in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.