Debug trace of cache memory requests
US12430224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jul 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.