Memory controller, memory controller control method, and memory system
US12430241B2 · kind B2 · utility
0Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Oct 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory controller includes a compression unit that compresses two or more determination voltage values for threshold voltages of a memory cell to a vector quantity, the memory cell being capable of storing three or more data values. The memory controller further includes a storing unit that stores the vector quantity into a memory region. The memory controller further includes a decompression unit that decompresses the stored vector quantity to provide the determination voltage values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.