Hybrid microprocessor and programmable logic device (PLD)-based architecture including inter processor communication
US12430265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 2, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.