VLSI placement optimization using self-supervised graph clustering
US12430485B2 · kind B2 · utility
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Key dates
| Filing date | Nov 2, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jul 4, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLSI placement optimization framework receives a cell connectivity representation and cell characteristics and uses self-supervised graph clustering to optimize cell cluster assignments for power, performance, and area (PPA). The framework provides cell clustering constraints as placement guidance to commercial placers. Specifically, graph learning techniques are used to formulate the PPA metrics as machine learning loss functions that can be minimized directly through gradient descent. The framework improves the PPA metrics at the placement stage and the improvements endure to the post-route stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.