Methods of designing layout of semiconductor device and methods for manufacturing semiconductor device using the same
US12430488B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Apr 17, 2024 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 17, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.