Self-reference storage structure and in-memory computing circuit
US12431175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Oct 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-reference storage structure includes: three transistors, including a first transistor T1, a second transistor T2, and a third transistor T3; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJ0 and a second magnetic tunnel junction MTJ1. The first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3. When the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.