Efficient Muller C-Element implementation for high bit-width asynchronous applications
US12431188B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jun 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.