Method of fabricating a semiconductor structure with improved dicing properties
US12431391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.