Hybrid CMOS micro-LED display layout
US12431478B2 · kind B2 · utility
0Cited by
36References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Jan 20, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described is a CMOS power plane including interleaving contact areas, alternating Vled and Vcat contact areas, on at least two long sides of the μLED display area. By this way, Vled and cathode current are injected uniformly along the four sides of the μLED display panel. A large cathode current distribution ring on Vled and Vcat circuits is used to distribute the current along the four sides of the panel. The current distribution ring surrounds a pixel die area. An insulated area may be included on the cathode current redistribution ring adjacent one of the of μbumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.