Power electronics assembly having vertically stacked transistors
US12431770B2 · kind B2 · utility
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13References
18Claims
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Assignee
Inventors
Key dates
| Filing date | Nov 5, 2020 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Aug 1, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T90/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses and systems provide technology that includes a first transistor, a second transistor stacked on the first transistor, at least one electrical conductor that is positioned between the first and second transistors and electrically connected to the first and second transistors, and a busbar that is electrically connected to the first and second transistors through the at least one electrical conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.