Capacitor voltage balancing techniques for multi-level dual active bridge converter
US12431814B2 · kind B2 · utility
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7References
18Claims
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Key dates
| Filing date | Sep 15, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 10, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/487
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Capacitor voltage balancing techniques are described for a 3-level 3-level dual-active-bridge converter that controls the duration of a zero voltage state of the low voltage (LV) and medium (MV) side transformer voltages based on a voltage difference between the upper and lower capacitors of both the LV and MV sides independently, the power delivered (P), and the LV and MV DC voltages. This control varies the angle to maintain the power requirement, which induces the additional voltage drop across the transformer inductance to produce the required current to flow through the capacitors and balance the capacitor voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.