Circuit and method for controlling a transistor
US12431885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Feb 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/307
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.