Semiconductor devices having parallel-to-serial converters therein
US12431901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Aug 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel-to-serial converter includes first to fourth input nodes configured to receive first to fourth data input signals, respectively, and an output node configured to output a data output signal. First to fourth logic circuits are provided, which are configured to electrically couple respective ones of the first to fourth input nodes one-at-a-time to the output node, in synchronization with first to fourth clock signals. The first logic circuit includes a first input circuit, a second input circuit, and an output circuit electrically coupled to the first and second input circuits. The output circuit includes a first pull-up transistor and a first pull-down transistor having drain terminals coupled to the output node, a second pull-up transistor connected between a source terminal of the first pull-up transistor and a first power supply node, and a second pull-down transistor connected between a source terminal of the first pull-down transistor and a second power supply node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.