Transmitting clock signals in network packets
US12431999B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/065
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock signal in a clock distribution network is transmitted using network packets with the clock signal embedded within a bit of the network packets. The network packets can include a preamble used to create phase alignment between a timing pulse and a bit position of a Start of Frame Delimiter (SFD) within the packet. The clock signal associated with the packet occurs when the SFD is detected. In one example, the SFD is detected when two consecutive bits of equal value are received and the timing of the clock signal is such that the clock signal occurs when the second consecutive bit is received. By including a clock signal within a packet, additional information can be transmitted with the clock signal. For example, authentication and validation information can be included, a time stamp, a message type, a frame check sequence, a clock status, a number of hops from the root, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.