Bit-length control for linear regression-based affine merge candidate derivation
US12432352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 5, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/59
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An example device for coding video data includes memory configured to store the video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce a bit length of one or more input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of subblocks. The one or more processors are configured to perform the linear regression operation and derive an affine motion model based on the performing the linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of the video data based on the affine motion model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.