Semiconductor structure and manufacturing method thereof
US12432932B2 · kind B2 · utility
0Cited by
5References
7Claims
0Family size
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Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 27, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the substrate, wherein a channel material of the vertical transistor includes an oxide semiconductor. A plurality of staggered contact pads connected to upper ends of the vertical transistors are formed on the vertical transistors, wherein a single contact pad is connected to the upper ends of an even number of vertical transistors. A magnetic tunnel junction is formed on the contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.