Semiconductor memory devices
US12432939B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Apr 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a substrate including an active pattern, the active pattern including first and second source/drain regions spaced apart from each other, a bit line that is electrically connected to the first source/drain region and crosses the active pattern, a storage node contact electrically connected to the second source/drain region, a spacer structure between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, an insulating pattern on the spacer structure and adjacent to the landing pad, and a liner between the insulating pattern and the landing pad. The insulating pattern may include an upper insulating portion and a lower insulating portion between the upper insulating portion and the spacer structure. The largest width of the lower insulating portion may be larger than the smallest width of the upper insulating portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.