Integrated structure of MOS transistors having different working voltages and method for manufacturing same
US12432961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Feb 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses an integrated structure of MOS transistors having different working voltages. A second spacer of a second MOS transistor having a middle second working voltage is formed by adding a third sub-spacer on the basis of a first spacer of a first MOS transistor having a relatively low first working voltage, and the first spacer is formed by stacking a first sub-spacer and a second sub-spacer. The thickness of the second spacer is adjusted via the third sub-spacer, so as to ensure that a GIDL leakage of the second MOS transistor under the second working voltage satisfies a requirement. The present application also discloses a method for manufacturing an integrated structure of MOS transistors having different working voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.