Semiconductor device having conductive portions in a groove and contacting a gate insulating layer
US12433004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Aug 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.