Semiconductor die with a vertical transistor device
US12433013B2 · kind B2 · utility
0Cited by
3References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | May 31, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/141
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a semiconductor die, including a vertical power transistor device, a pull-down transistor device, and a capacitor. The pull-down transistor device is connected between a gate electrode of the vertical power transistor device and a ground terminal and connects the gate electrode to the ground terminal in a conducting state. The capacitor is connected between one of the load terminals of the vertical power transistor device and the control terminal of the pull-down transistor device and capacitively couples the one load terminal to the control terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.