Array substrate and manufacturing method for the same, display panel
US12433028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/471
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application provides an array substrate, a manufacturing method for the same, and a display panel. The array substrate includes a display area and a non-display area connected to the display area, and the display area includes a plurality of sub-pixels arranged in an array. The non-display area includes at least one polysilicon transistor, each of the sub-pixels includes an oxide transistor and a pixel electrode. A gate of the oxide transistor as well as a first electrode and a second electrode of the polysilicon transistor are arranged in a same layer; an active layer of the oxide transistor and the pixel electrode are arranged in a same layer, and are in contact with each other. The active layer of the oxide transistor includes an oxide semiconductor material, and the pixel electrode includes an oxide conductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.