Digital frequency-control circuit

US3935538A · kind A · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Harald Kizler
• Bernd Przybyla · Schwieberdingen, DE
• Peter Schmidt · Schwieberdingen, DE

Key dates

• Filing date: Aug 21, 1974
• Grant date: Jan 27, 1976
• Expiry date: Aug 21, 1994

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B62D33/0612
• WIPO field: Transport
• WIPO sector: Mechanical engineering

Abstract

Clock pulses are multiplied by a ratio less than 1 of which the numerator is controlled by a reversible counter. The multiplier output pulses initiate new countdown cycles of a second counter beginning with the clock pulse following the onset of an input frequency pulse and ending with the clock pulse following the onset of the next input frequency pulse. The state of the count at the end of the cycle determines whether the reversible counter will be left unchanged, advanced, or counted back and hence, whether the multiplier output frequency will be left unchanged, increased or reduced. The initial countdown value of the second counter is provided by a long term store which determines the frequency multiplication ratio. The circuit is usable to multiply a variable input frequency in a vehicle brake anti-lock system.