Segmented parallel rail paths for input/output signals
US3936812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1974 |
| Grant date | Feb 3, 1976 |
| Priority date | — |
| Expiry date | Dec 30, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.