Four quadrant multiplying divider using three log circuits
US3940603A · kind A · utility
6Cited by
4References
19Claims
0Family size
Inventor
Key dates
| Filing date | Jul 2, 1974 |
| Grant date | Feb 24, 1976 |
| Priority date | — |
| Expiry date | Jul 2, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three log circuits are fed by respective x, y and z inputs, along with predetermined interconnections therebetween. The outputs from the log circuits are log z, log (x+z) and log (y+z). These outputs are fed to summing and anti-log circuits to derive the equation (xy)/z + x + y + z. A second summing circuit is provided for substracting the three variables from the resultant output so that (xy)/z is finally derived.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.