Data processing unit having a plurality of hardware circuits for processing data at different priority levels
US3940745A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1974 |
| Grant date | Feb 24, 1976 |
| Priority date | — |
| Expiry date | Apr 26, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing unit having a plurality of hardware data processing circuits each one including a program counter register for addressing the microinstructions, an accumulator register and an addressing register for storing the addressing of the operands of the microinstructions. Means are provided for switching the CPU from the hardware data processing circuits having a predetermined priority level to the hardware data processing circuits having a less priority level, by executing a particular microinstruction, which includes information either about the changing of the priority level or about the memory address of the starting microinstruction of the microprogram to be executed on the less priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.