Multi-level digital filter
US3946214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1974 |
| Grant date | Mar 23, 1976 |
| Priority date | — |
| Expiry date | Sep 17, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-level digital filter system applicable to modems is provided. The incoming data is read serially into M shift registers and read out in parallel by M further shift registers under the control of an M-bit clock, where M=log.sub.2 N and N is the number of levels. After appropriate conditioning by a logic control circuit, the parallel outputs are filtered separately by M digital shaping filters. The shaping filters each comprise a chain of shift registers the outputs of which are weighted by a resistor network and summed to produce a desired time response, which in an exemplary embodiment is the inverse Fourier transform of an ideal low-pass filter. Summing of the filter outputs produces an N-level signal. Specific examples of three-, four-, five-, six- and eight-level systems are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.