Multi-emitter transistor having heavily doped N+ regions surrounding base region of transistors
US3946425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1974 |
| Grant date | Mar 23, 1976 |
| Priority date | — |
| Expiry date | May 14, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/613
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device in which a plurality of regions each having a semiconductor element such as a PN junction diode and a transistor are isolated electrically from one another by PN junctions formed between the respective regions and a semiconductor isolation region, gold is introduced into the regions having the semiconductor elements and the isolation region while at least one diffused region heavily doped, for example, with phosphorus is formed in the isolation region adjacent to the region having the PN junction diode or the transistor thereby to prevent the breakdown voltage of the backwardly biased PN junction in the diode or the transistor from decreasing. Further by surrounding all the transistors, at least in one of which gold is diffused, formed in one integrated circuit with heavily doped N.sup.+-type regions an integrated circuit with transistors having a small variation in current amplification factor is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.