Digital delay line correlator
US3947672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1972 |
| Grant date | Mar 30, 1976 |
| Priority date | — |
| Expiry date | Mar 14, 1992 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The correlator disclosed herein detects in a stream of input pulses a plurality of sequences of time spaced signals, each of the plurality of sequences having a different one of a plurality of pulse repetition intervals disposed within a given pulse repetition interval range. This is accomplished by clocking the input pulses into a first shift register by a first clock pulse having a given frequency. N groups of n bistable stages (N being an integer greater than one and n being an integer greater than zero) are disposed at different spaced time positions along the first register corresponding to the pulse repetition intervals and the pulse repetition interval range. First logic circuitry is coupled to each of the N groups of n stages to provide an output pulse when the time spaced pulses of the plurality of sequences of time spaced pulses are simultaneously present at appropriate ones of the n stages of a given number of the N groups of n stages. A second shift register receives on its input stage the output pulse from the first logic circuitry. The output pulse is clocked through the second register by a second clock pulse having the given frequency but phase shifted relative to t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.