Packaging and interconnection for superconductive circuitry
US3949274A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 1974 |
| Grant date | Apr 6, 1976 |
| Priority date | — |
| Expiry date | May 30, 1994 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional micro electronic module packaged for reduced signal propagation delay times includes a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.