D. C. Stable semiconductor memory cell
US3949383A · kind A · utility
18Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1974 |
| Grant date | Apr 6, 1976 |
| Priority date | — |
| Expiry date | Dec 23, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.