Successive-approximation analog-to-digital converter using Josephson devices
US3949395A · kind A · utility
10Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1974 |
| Grant date | Apr 6, 1976 |
| Priority date | — |
| Expiry date | Aug 28, 1994 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/827
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparison means has plural Josephson devices each controlled by an analog input current and an opposing subtraction current. A subtraction means has a series circuit of Josephson devices arranged in groups, each group being switched by one of the comparison devices. The subtraction current is proportional to the number of devices switched in the series circuit. An output means has a string of Josephson devices each providing an output bit from one of the comparison devices. Fixed bias currents control the effective thresholds of the comparison devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.