Logic level translator
US3959666A · kind A · utility
14Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1974 |
| Grant date | May 25, 1976 |
| Priority date | — |
| Expiry date | Jul 1, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic level translator uses a current switch, a current source and a plurality of cathode followers to convert T.sup.2 L and DTL level binary signals into CML and ECL level binary signals. The translator provides isolation between the T.sup.2 L ground and the CML ground so that noise in the CML signals is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.