Fixed point to floating point conversion in an electronic computer
US3961170A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1974 |
| Grant date | Jun 1, 1976 |
| Priority date | — |
| Expiry date | Apr 17, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital electronic computer which comprises a memory including a first and a second register, the first register is receptive of a number to be converted from fixed to floating point notation and the second register is receptive of a significant zero digit with an associated decimal point. Shifting means including a register is operable to shift the contents of either register and aligning means is operable to cause shifting of the second register until the decimal point stored therein is aligned with the decimal point in the first register. Indicating means indicates whether the number stored in the first register is greater or less than one and the shifting means next begins shifting the contents of one or the other of the registers when the number is indicated greater or less than one respectively. A control means includes a detecting means for stopping the shifting means when the decimal point of the second register becomes aligned with the location of the next higher order with respect to the highest significant digit of the first register. The control means also includes counting means which is incremented or decremented by one for each shifting operation in dependence o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.