Inverter with minimum skew
US3962589A · kind A · utility
5Cited by
1References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1975 |
| Grant date | Jun 8, 1976 |
| Priority date | — |
| Expiry date | Feb 10, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.