Oxide isolated integrated injection logic with selective guard ring
US3962717A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1974 |
| Grant date | Jun 8, 1976 |
| Priority date | — |
| Expiry date | Oct 29, 1994 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors incorporates the steps of growing a doped epitaxial layer of single-crystal silicon on a silicon substrate, applying a first insulation material in a selected pattern over the epitaxial layer to define oxide-isolation regions and device regions, etching grooves in the areas in which oxide-isolation regions will be formed, applying a self-aligned base insulation material over those portions of the interface between the first insulation material and the grooves which bound the region between the base of any vertical bipolar transistor to be formed and the emitter of any lateral bipolar transistor to be formed, applying an impurity of a conductivity type opposite to the conductivity type of the epitaxial layer to those groove areas not covered by the self-aligned base insulation material, the impurity serving to prevent emitter-to-collector inversion along the wall of the base of any vertical bipolar transistor without shorting the emitter and collector of any lateral bipolar transistor, forming oxide-isolation regions in the grooves and forming the vertic…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.