MOS speed-up circuit
US3965460A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 1975 |
| Grant date | Jun 22, 1976 |
| Priority date | — |
| Expiry date | Jan 2, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A speed-up circuit, which may be used to speed up the sensing of a bit-sense line of an MOS RAM, includes a crosscoupled latch circuit having an output suitable for coupling to an output circuit for the RAM. A plurality of bit-sense lines of the RAM storage array are coupled to load circuitry for one side of the latch circuit. When partial discharging of a bit-sense line by a selected memory cell occurs, the latch circuit switches state and provides feedback internal to the latch circuit and other feedback external to the latch circuit to aid the selected memory storage cell in discharging a bit-sense line much more rapidly than could have been achieved by the action of the selected storage cell alone, and also assures complete discharging of the bit-sense line, which avoids destroying stored data in the selected memory cell during a refresh cycle. The external feedback is coupled to discharge devices connected to the various bit-sense lines serving various sections of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.