Circuit for automatically correcting the timing of clock pulse in self-clocked pulse signal decoders
US3968328A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1974 |
| Grant date | Jul 6, 1976 |
| Priority date | — |
| Expiry date | Dec 18, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In dynamic modulation (D.M.) of non-return-to-zero pulse signals, the only condition under which the D.M. signal would remain in the same state, either 1 or 0, for two consecutive pulse intervals is when the NRZ signal includes the sequence 101. Two sampling signals at the proper clock repetition rate are generated from the D.M. signal by the decoder and are successively used to sample the D.M. signal and to sample the signal resulting from the first sampling. Information of the state of the D.M. signal at the time of the first sampling is retained to be compared with the state of the D.M. signal at a later time, and the state of one of the compared signals is separately compared with the state of a signal between the first-compared signals. If the wrong clock pulses midway between the correct clock pulses are used in making the comparisons, a correction signal will be generated in the last half of the second consecutive pulse interval in which the D.M. signal remains in the same state. This correction signal is used to adjust the clock pulse selector to select the correct pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.