Digital time-off-event encoding system
US3971920A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1975 |
| Grant date | Jul 27, 1976 |
| Priority date | — |
| Expiry date | May 5, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital storage system provides an economical means by which binary data words describing a series of events occurring randomly in time can be stored during a recording period and later retrieved in their sequence of occurrence with the time-of-event information preserved. A first recirculating shift register memory having arbitrarily great length, such as 4096 cells, each cell capable of storing a parallel binary data word such as 6 (or N bits), a second recirculating shift register memory of equal length, similarly capable of storing parallel binary error codes, and a cell counter having a counting capacity equal to the numerical length of said shift register memories are clocked in synchronism and comprise the storage medium. A clock control circuit provides shift clock pulses to said shift register memories and cell counter at basic clock intervals such as 16 microseconds during data absence, but alternatively provides a "premature" shift clock pulse when a "data ready" flag appears, causing the entry of a data word into said first shift register memory. An error encoder circuit provides a binary count of sub-intervals of the basic clock interval, such as zero through fifteen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.