Flip-flop false output rejection circuit
US3971960A · kind A · utility
14Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1975 |
| Grant date | Jul 27, 1976 |
| Priority date | — |
| Expiry date | Mar 5, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.