Logic level translator
US3974402A · kind A · utility
18Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1975 |
| Grant date | Aug 10, 1976 |
| Priority date | — |
| Expiry date | Mar 26, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.