Integrated circuit interface stage for high noise environment
US3974404A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1975 |
| Grant date | Aug 10, 1976 |
| Priority date | — |
| Expiry date | Mar 26, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An interface circuit for integrated circuit devices which prevents deleterious injection of minority carriers into the substrate during overvoltages applied to a terminal of the integrated circuit. A lateral PNP transistor formed in an N-type region has its base connected to a bias circuit and its collector connected to a load circuit and its emitter connected to a current source having a P-type electrode. The emitter is also connected to a first terminal of the integrated circuit. If the first terminal is connected to a signal wire having large negative noise pulses thereon, the emitter-base junction of the lateral PNP transistor will become reverse biased during the negative pulses, thereby preventing the injection of minority carriers into the P-type substrate in which the integrated circuit is fabricated. If the terminal is connected to a second terminal of a second integrated circuit having therein a lateral PNP transistor having its base connected to a control circuit and its collector connected to a load circuit, the first and second lateral PNP transistors and the current source form a differential amplifier, which provides a low impedance to noise impulses applied to the t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.