Method of fabricating multi-layer printed circuit board
US3977075A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1975 |
| Grant date | Aug 31, 1976 |
| Priority date | — |
| Expiry date | Jun 17, 1995 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
According to one aspect of the disclosure, a planar substrate receives a plurality of conductive posts therein, which posts include an offset medial portion having a laterally projecting notch portion. Certain posts are arranged with their notch portions in coplanar relationship and in latching registration with an interior sidewall portion of a housing received over the posts. Accordingly, the housing provides an insulating receptacle shroud for the posts and is latchingly retained in place without a need for attachment to the substrate. The shroud is also provided with card guides connected thereto by integral hinge portions enabling alignment of, and reducing twisting and warping of, the card guides. The card guides are additionally coupled together with rails further reducing twisting and warping of the guides. The terminals are advantageously mounted in strip form for ease in manufacture and assembly to the substrate. According to another aspect of the disclosure, a plurality of discrete electrically conductive posts are initially connected on selected center spacings to a common carrier strip without interconnecting portions between adjacent posts. A portion of the carrier st…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.