Discrete analog processing system including a matrix of memory elements
US3979582A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1974 |
| Grant date | Sep 7, 1976 |
| Priority date | — |
| Expiry date | Sep 17, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and being programmed so that the output of a CCD tap is multiplied by a particlar factor. In particular, the MNOS memory devices are disposed in a matrix of rows and columns. The outputs of the MNOS memory devices of each row are summed and the row output signal e(t- ##EQU1## WHERE W.sub.k is the weighting factor associated with the K.sup.th MNOS memory device are applied to corresponding inputs of a parallel-to-series converter taking the form of a CCD. The parallel-to-series converter then is enabled to serially read out the row outputs. The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device. Positive and negative weighting factors are implemented by using first and second MNOS memory elements for each tap of the CCD, whereby depending upon the program incorporated into the system, one of the first and sec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.