Split memory array sharing same sensing and bit decode circuitry
US3983544A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1975 |
| Grant date | Sep 28, 1976 |
| Priority date | — |
| Expiry date | Aug 25, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split random access memory array is integrated with a read only storage array and shares the same sense and bit decode circuitry. Each bit line of the integrated array is provided with an isolation switch between the random access and read only portions. The switch conducts when reading the read only portion but does not conduct (isolates) when writing or reading the random access portion. The isolation switch also permits the initialization of the shared differential sensing latch and facilitates the rapid writing and reading of the random access portion by removing the bit line loading due to the read only portion on such occasions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.