High withstand voltage semiconductor device with shallow grooves between semiconductor region and field limiting rings with outer mesa groove
US3984859A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1975 |
| Grant date | Oct 5, 1976 |
| Priority date | — |
| Expiry date | Jan 3, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
In a high-withstand-voltage (high-breakdown voltage) semiconductor device in which the main PN junction is of planar structure and a field limiting ring region is provided outside and around the exposed end of the main PN junction, a groove is formed between the main region to form the main PN junction and the field limiting ring region, the bottom of which groove is shallower than that of each of the regions and in the surface of which groove the end of the main PN junction and one of the ends of the PN junction between the field limiting ring region and the substrate are exposed, and the other end of the PN junction between the field limiting ring region and the substrate is exposed in the surface of another groove whose bottom is deeper than that of the field limiting ring region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.