CMOS digital circuits with resistive shunt feedback amplifier
US3986041A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1974 |
| Grant date | Oct 12, 1976 |
| Priority date | — |
| Expiry date | Dec 20, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.