High density logic array
US3987287A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1974 |
| Grant date | Oct 19, 1976 |
| Priority date | — |
| Expiry date | Dec 30, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end. The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.