Binary incrementer circuit
US3989940A · kind A · utility
18Cited by
4References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1975 |
| Grant date | Nov 2, 1976 |
| Priority date | — |
| Expiry date | Mar 20, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An incrementer circuit, wherein a "1" is added to binary input information of n digits to provide binary output information, characterized in that output information of the lowest digit is produced as inverted input information by an inverter circuit, and that output information of each of the second-lowest to nth digits is produced by passing either input information of the particular digit or its inverted signal from an inverter circuit through a corresponding one of transfer gate transistor paths, which are controlled by the information of the digits lower than the particular digit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.